As the dimension of CMOS (Complementary Metal Oxide Semiconductor) devices continuously scaling-down, the dielectric constant k-value of dielectric used in the interconnection has also been continuously reducing, and novel dielectric materials have been constantly sought, developed from the primely simplex silicon oxide to FSG and SiOC, until to the porous ultra low-k films under 45 nm node.
However, as the k-value of film reducing, more area is required for integrating capacitor C with same size into the interconnection, and the waste of area results in increasing cost of manufacturing chips.